In scaled complementary metal–oxide–semiconductor (CMOS) processes, op-amp-based switched-capacitor photodiode readouts face intrinsic-gain and bandwidth limitations, motivating comparator-based switched-capacitor (CBSC) architectures that use fast comparators and current-driven charge transfer for high-speed, low-power operation. This paper introduces a novel CBSC circuit architecture designed to enhance photodiode readout performance. Unlike conventional designs that rely on high-gain operational amplifiers, the proposed approach leverages a nonlinear current source to trigger a comparator, enabling virtual-ground formation and high-speed charge transfer. The circuit was implemented and evaluated via HSPICE simulations in a 0.18 μm CMOS technology and demonstrated reliable operation at frequencies up to 100 MHz. Key innovations include a non-linear current-source scheme to accelerate the photodiode voltage response and a reset mechanism that further reduces operational delay. Detailed simulation results confirm robust, power-efficient operation with tolerance to temperature and process variations. These findings suggest that the proposed CBSC circuit is a promising, energy-efficient alternative for next-generation analog and mixed-signal sensor applications where high-speed pixel response is critical.