News and Announcements
ORIGINAL RESEARCH ARTICLE
Digital-like built-in defect-oriented test for analog-mixed signal circuits
Show Less
1 Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa,
United States of America
Submitted: 29 July 2024 | Accepted: 14 September 2024 | Published: 18 November 2024
© 2024 by the Author(s). This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution -Noncommercial 4.0 International License (CC-by the license) ( https://creativecommons.org/licenses/by-nc/4.0/ )
Abstract
In this paper, we present a novel digital-like defect-oriented built-in self-test (BIST) methodology for analog and mixed-signal (AMS) circuits. The core idea of this approach centers around the segmentation of complex AMS circuits into smaller, more manageable units for analysis. Emphasizing resource utilization efficiency, we highlight the necessity of employing purely digital circuits for both injectors and monitors within the BIST framework. We demonstrate the effectiveness of this approach through the development of a BIST system for a 12-bit successive approximation register analog-to-digital converter (SAR ADC). Notably, our methodology achieves 100% defect coverage without introducing additional BIST circuitry for subcircuit testing, relying solely on digital monitors for sampling switch evaluation. Furthermore, our proposed approach incurs minimal area overhead, resulting in a fast and comprehensive defect-oriented BIST solution. This versatile test method can be deployed post-manufacturing or in-field, offering flexibility in its application timing.
Keywords
Analog and mixed signal circuits
Defect-oriented test
Built-in self-test
Defect coverage
Analog-to-digital converter
Funding
This work was financially supported by Jerry Junkins Chair Endowment grant provided by Iowa State University organization, and 2810-047 and 2810-084 grants from Semiconductor Research Corporation (SRC).
Conflict of interest
The authors declare that they have no competing interests.
References
- Dobbelaere W, Colle F, Coyette A, et al. Applying Vstress and Defect Activation Coverage to Produce Zero-defect Mixed-signal Automotive ICs. In: Proceedings of the 2019 IEEE International Test Conference (ITC). Washington, DC, USA: IEEE; 2019. p. 1-4. doi: 10.1109/ITC44170.2019.9000123
- Koopman P, Wagner M. Autonomous vehicle safety: An interdisciplinary challenge. IEEE Intell Transp Syst Mag. 2017;9(1):90-96. doi: 10.1109/MITS.2016.2583491
- Sunter S. Analog Fault Simulation - A Hot Topic! In: Proceedings of the 2020 IEEE European Test Symposium (ETS). Tallinn, Estonia: IEEE; 2020. p. 1-5. doi: 10.1109/ETS48528.2020.9131581
- Saikiran M, Ganji M, Chen D. Digital Defect-oriented Test Methodology for Flipped Voltage Follower Low Dropout (LDO) Voltage Regulators. In: Proceedings of the 2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI). Porto Alegre, Brazil: IEEE; 2022. p. 1-6. doi: 10.1109/SBCCI55532.2022.9893243
- Xu L, Huang J, Wang H, Long B. A novel method for the diagnosis of the incipient faults in analog circuits based on LDA and HMM. Circuits Syst Signal Process. 2010;29(4):577-600. doi: 10.1007/s00034-010-9160-1
- Bailey B. Why Analog Designs Fail. Semiconductor Engineering. Available from: https://semiengineering. com/making-analog-more-reliable [Last accessed on 2023 Sep 01].
- Sekyere M, Saikiran M, Chen D. All-digital Low-cost Built-in Defect Testing Strategy for Operational Amplifiers with High Coverage. In: Proceedings of the 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS). Torino, Italy: IEEE; 2022. p. 1-5. doi: 10.1109/IOLTS56730.2022.9897224
- Sunter S. Efficient Analog Defect Simulation. In: Proceedings of the 2019 IEEE International Test Conference (ITC). Washington, DC, USA: IEEE; 2019. p. 1-10. doi: 10.1109/ITC44170.2019.9000141
- P2427 - Standard for Analog Defect Modeling and Coverage. Available from: https://standards.ieee.org/project/2427. html [Last accessed on 2020 Dec 16].
- Pavlidis A, Louërat MM, Faehn E, Kumar A, Stratigopoulos HG. SymBIST: Symmetry-based analog and mixed-signal built-in self-test for functional safety. IEEE Trans Circuits Syst I Regul Pap. 2021;68(6):2580-2593. doi: 10.1109/TCSI.2021.3067180
- Das SR, Zakizadeh J, Biswas S, et al. Testing analog and mixed-signal circuits with built-in hardware-a new approach. IEEE Trans Instrum Meas. 2007;56(3):840-855. doi: 10.1109/TIM.2007.894223
- Saikiran M, Sekyere M, Ganji M, Yang R, Chen D. Low-cost defect simulation framework for analog and mixed signal (AMS) circuits with enhanced time-efficiency. Analog Integr Circ Sig Process. 2023;117:73-94. doi: 10.1007/s10470-023-02167-7
- Saikiran M, Ganji M, Chen D. A Time-efficient Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits. In: Proceedings of the 2022 35th SBC/SBMicro/IEEE/ ACM Symposium on Integrated Circuits and Systems Design (SBCCI). Porto Alegre, Brazil: IEEE; 2022. p. 1-6. doi: 10.1109/SBCCI55532.2022.9893224
- Liu Z, Chaganti SK, Chen D. Improving time-efficiency of fault-coverage simulation for MOS analog circuit. IEEE Trans Circuits Syst I Regul Pap. 2018;65(5):1664-1674. doi: 10.1109/TCSI.2017.2751561
- Saikiran M, Ganji M, Chen D. Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage. In: Proceedings of the 2020 IEEE International Test Conference (ITC). Washington, DC, USA: IEEE; 2020. p. 1-10. doi: 10.1109/ITC44778.2020.9325226
- Saikiran M, Ganji M, Chen D. Robust Built-in Defect Detection for Low Drop-out Regulators Using Digital Mismatch Injection. In: Proceedings of the 2022 IEEE International Symposium on Circuits and Systems (ISCAS). Austin, TX, USA: IEEE; 2022. p. 1580-1584. doi: 10.1109/ISCAS48785.2022.9937644
- IEEE Draft Standard for Analog Defect Modeling and Coverage. IEEE P2427/D0.35; 2022. Available from: https:// www.ieee standards [Last accessed on 2024 Jun 15].
- Aksin D, Al-Shyoukh M, Maloberti F. Switch bootstrapping for precise sampling beyond supply voltage. IEEE J Solid- State Circuits. 2006;41(8):1938-1943. doi: 10.1109/JSSC.2006.875305
- Huang CP, Lin JM, Shyu YT, Chang SJ. A systematic design methodology of asynchronous SAR ADCs. IEEE Trans Very Large Scale Integr Syst. 2016;24(5):1835-1848. doi: 10.1109/TVLSI.2015.2494063
- De Lima Kastensmidt FG, Neuberger G, Hentschke RF, Carro L, Reis R. Designing fault-tolerant techniques for SRAM-based FPGAs. IEEE Des Test Comput. 2004;21(6):552-562. doi: 10.1109/MDT.2004.85
- Sunter S, Wolinski M, Coyette A, Vanhooren R, Dobbelaere W, Xama N. Quick Analyses for Improving Reliability and Functional Safety of Mixed-signal ICs. In: Proceedings of the 2020 IEEE International Test Conference (ITC). Washington, DC, USA: IEEE; 2020. p. 1-10. doi: 10.1109/ITC44778.2020.9325230
- McAndrew CC, Hoseini M, Braswell B, Garrity DA. Improvements to statistical characterization and modeling, and a caution to be aware of spurious correlation in statistical simulation. IEEE Trans Comput Aided Des Integr Circuits Syst. 2023;42(7):2252-2263. doi: 10.1109/TCAD.2022.3216550
- Wang J, Goh WL. A 13.5-MHz Relaxation Oscillator with ±0.5% Temperature Stability for RFID Application. In: Proceedings of the 2016 IEEE International Symposium on Circuits and Systems (ISCAS). Montreal, QC, Canada: IEEE; 2016. p. 2431-2434. doi: 10.1109/ISCAS.2016.7539083
- Paidimarri A, Griffith D, Wang A, Burra G, Chandrakasan AP. An RC oscillator with comparator offset cancellation. IEEE J Solid-State Circuits. 2016;51(8):1866-1877. doi: 10.1109/JSSC.2016.2559508
- Sebastiano F, Breems L, Makinwa K, Drago S, Leenaerts D, Nauta B. A Low-voltage Mobility-based Frequency Reference for Crystal-less ULP Radios. In: Proceedings of the ESSCIRC 2008 - 34th European Solid-State Circuits Conference. Edinburgh, UK: IEEE; 2008. p. 306-309. doi: 10.1109/ESSCIRC.2008.4681853