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ORIGINAL RESEARCH ARTICLE

A novel approach for designing high-accuracy approximate signed multipliers

Faraz Baraati1 ,  Abdolah Amirany2* ,  Milad Tanavardi Nasab3 ,  Kian Jafari4,5 ,  Reza Ghaderi1
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1 Faculty of Electrical Engineering, Shahid Beheshti University, Tehran, Iran
2 Department of Electrical and Computer Engineering, School of Engineering and Applied Science, The George Washington University, Washington, DC, United States of America
3 Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, Tennessee, United States of America
4 Interdisciplinary Institute for Technological Innovation (3IT), Université de Sherbrooke, Sherbrooke, Quebec, Canada
5 Faculty of Engineering, Université de Sherbrooke, Sherbrooke, Quebec, Canada
DP 2024, 1(1), 3882 https://doi.org/10.36922/dp.3882
Submitted: 6 June 2024 | Accepted: 30 July 2024 | Published: 8 October 2024
© 2024 by the Author(s). This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution -Noncommercial 4.0 International License (CC-by the license) ( https://creativecommons.org/licenses/by-nc/4.0/ )
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Abstract

Signed multiplication is crucial for performing arithmetic operations with positive and negative numbers. It has applications in signal processing, digital image processing, communication, cryptography, neural network hardware accelerators, and more. Until today, to multiply signed numbers, the data are often converted to unsigned format, and the sign is added to the final product. This method imposes high hardware requirements for data conversion and presents challenges in designing approximate multipliers. This paper proposes a novel method for designing approximate signed multipliers that eliminate the need for data conversion, thereby reducing the overall hardware requirement while maintaining accuracy. Comprehensive evaluations at the system level using MATLAB and circuit-level performance analysis using HSPICE demonstrate that the proposed approach offers a successful trade-off between area overhead, power consumption, and accuracy. The achieved trade-off makes the proposed method a promising solution for optimizing digital circuits in various applications such as artificial intelligence and image processing.

Graphical abstract
Keywords
Signed multiplication
Approximate multiplier
Low-power design
Neural networks
Funding
None.
Conflict of interest
Abdolah Amirany is an Editorial Board Member of this journal but was not involved, directly or indirectly, in the editorial or peer-review process for this paper. Separately, the other authors declared no known competing financial interests or personal relationships that could have influenced the work reported in this paper.
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